Internal RAM Structure of 8051

Introduction

In this article, we are discussing about the Internal RAM structure of 8051. 8051 Microcontroller is a 8-bit microcontroller. It contains 128 byte of internal RAM. This internal RAM of 8051 is divided into three sections which are followings-

• 32 bytes – Register Bank
• 16 bytes – Bit Addressable Area
• 80 bytes – Scratch Pad Area & SFR

Below shows the Internal Architecture of 8051 RAM.

RAM Architecture of 8051

About the Sections of RAM Architecture

32 Byte – Register Bank

There are four register banks in the RAM. Each register bank contains 8 registers of 1 byte. So a total of 32 registers in the register bank by default register bank 0 is selected to change the registered bank. We have to set the value of two register selection bits in the PSW register.

16 Byte – Bit Addressable Area

In RAM of 8051, there are 16 byte areas in which 128 bit we can accessed by suitable instruction. The address range of bits addressable area is 00th ( LSB of first byte of 20h ) to 7Fh ( MSB of last byte of 2Fh )

80 Byte – Scratch Pad Area & SFR

Remaining 80 bytes are general purpose area which are shared with DATA and SFR (Special Function Register) upper 128 byte of RAM accessed indirect addressing while SFR accessed by direct addressing only. SFR contains special registers like ACC, B, IE, IP, etc.

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